1. Field of the invention
The invention concerns a mail franking machine which prints stamps and totalizes the value of said stamps.
2. Description of the prior art
A conventional machine of this kind comprises:
a motor and drums carrying digits in relief for printing a stamp; PA1 a microprocessor for controlling said motor and for totalling the values of stamps printed; PA1 position encoders connected to respective drums to translate into binary words the values of the digits printed on the stamp; PA1 manually operable switches; PA1 a first interface controlled by instructions from said microprocessor for scanning and transmitting to said microprocessors said values translated by said encoders and the states of said switches; PA1 a first interface controlled by instructions from said microprocessor for scanning and transmitting to said microprocessors said values translated by said encoders and the states of said switches; PA1 a second interface controlled by instructions from said microprocessor for switching the power supply of said motor. PA1 a motor and drums carrying digits in relief for printing a stamp; PA1 a microprocessor for controlling said motor and for totalling the values of stamps printed; PA1 position encoders connected to respective drums to translate into binary words the values of the digits printed on the stamp and the states of manually operable switches; PA1 manually operable switches; PA1 a first interface controlled by instructions from said microprocessor for scanning and transmitting to said microprocessor said values translated by said encoders and the states of said switches; and PA1 a second interface controlled by instructions from said microprocessor for switching the power supply of said motor; PA1 in which machine said first interface comprises an application specific integrated circuit including means for scanning and transmitting to said microprocessor said values translated by all said encoders and the states of all said switches of said machine in response to receiving a single instruction from said microprocessor. PA1 a bus connected to said microprocessor; PA1 means for filtering signals sent by said microprocessor; PA1 means for parallelizing binary data received serially; PA1 address decoder means; PA1 means for detecting a start of transaction signal and an end of transaction signal sent by said microprocessor; PA1 and, specific to said second interface: PA1 means for memorizing the status of the motor power supply; and PA1 at least part of a switching amplifier for switching the motor power supply. PA1 mutually exclusive operating phases: PA1 an idle phase after each power on or after an idle command sent by said sequencer itself or by said microprocessor; PA1 an activation phase when said application specific integrated circuit receives a start of transaction signal, said phase enabling detection of an address specific to said application specific integrated circuit and a bit representing either an instruction to scan and transmit said values translated by said encoders and said states of said switches or an instruction to switch the power supply of said motor; PA1 a scan and transmit phase after an activation phase if said application specific integrated circuit receives, after its address, a bit representing an instruction to scan and transmit said values translated by said encoders and said states of said switches, said phase being followed by a return to said idle phase; and PA1 a motor control phase following an activation phase when said application specific integrated circuit receives, after its address, a bit representing an order to switch the power supply of said motor on or off.
It is known to divide these subsystems between two printed circuit boards. A main board carries the microprocessor and a first part of the second interface. An interface board carries the first interface, the position encoders, the switches and a second part of the second interface. The two boards are connected by five-way connectors carrying: a reference potential, an electronic circuit power supply potential, a motor control signal and a two-wire serial transmission bus using the I2C protocol, for example. The microprocessor controls transactions between the two boards. One bus line carries clock pulses timing transmission and the other carries binary data in either direction. The bus carries instructions which command scanning and transmission of the values translated by the encoders and the states of the switches, and transmits data in response to such instructions.
The first interface comprises two general purpose integrated circuits available through ordinary commercial channels: a serial input-output circuit and a decoder. These circuits are used to scan a matrix of conductors in which the encoders and the switches set up variable connections between rows and columns. The want of outputs on these circuits makes it necessary to use twelve diodes to connect six outputs of the decoder to the twelve columns of the matrix without compromising the independence of the columns.
The second interface switches the motor power supply and comprises an address decoder and a latching register on the main board and a power transistor and a pre-amplifier transistor on the interface board. The motor control line carries a DC voltage provided by an output of the latching register and controlling the preamplifier transistor directly. One implementation of a prior art machine interface board will be described in more detail later.
The interface board of a prior art machine has the advantage of using only generally available general purpose integrated circuits. Their number is small (two) but it is desirable to reduce the number to reduce the manufacturing cost of the machine (printed circuit, assembly, inspection cost). It is not possible to reduce the number of integrated circuits using a single commercially available integrated circuit as there is no general purpose integrated circuit available to provide all of the functions of the first interface and some or all of the functions of the second interface. It is therefore necessary to consider the use of an application specific integrated circuit (ASIC). It is possible to integrate into a single integrated circuit the twelve diodes, the serial input-output circuit and a decoder. The new machine would then have the same performance and the same drawbacks as the prior art machine, except that the overall size and cost would be reduced.
The prior art machine has the following drawbacks. To scan the value translated by each encoder it is necessary to send from the microprocessor to the inputoutput circuit a write instruction essentially comprising two bytes and then to send from the microprocessor to the input-output circuit a read instruction essentially consisting of one byte and finally to send from the input-output circuit to the microprocessor a data byte. Four bytes are therefore transmitted in one direction or the other to scan the state of a single encoder. Also, each instruction sent by the microprocessor is preceded by a characteristic start of transaction signal and is followed by a characteristic end of transaction signal.
Scanning four encoders requires four scan cycles initiated by four instructions from the microprocessor.
The manually operated switches constitute two groups separate from the encoders and for which a fifth and sixth scanning cycle are performed and a fifth and sixth data byte are transmitted. Finally, the scanning of all the encoders and switches is followed by idling of all the columns of the matrix, which entails configuring the input-output circuit by means of a write instruction so that none of the matrix columns is scanned by the decoder In all, 26 bytes are transmitted on the data line to scan four encoders and four switches.
To eliminate the effect of encoder and switch contact bounce, a scan is commanded every ten milliseconds. In an embodiment in which the minimum period of the bus clock timing transmission is ten microseconds, the minimum time needed to scan four switches and four encoders is 2.5 milliseconds. The microprocessor therefore devotes one quarter of its time to carrying out the scanning. Also, a non-negligible current flows in the columns of the matrix representing an encoder while the latter is being scanned. Consequently, the overall scanning period has a direct effect on the quantity of energy drawn from the power supply of the electronic circuits of the machine. Also, this scanning mode requires a relatively complex program to be stored in the program store of the microprocessor.
The prior art machine has another drawback due to the want of outputs on the decoder. Using diodes to connect the matrix columns to the decoder output reduces by around 0.7 volt the noise immunity of the input-output circuit ports when they are configured as inputs.
The use of two different processes to transmit motor instructions and scanning instructions leads to the addition of a dedicated line linking the two boards of the machine, increasing by one the number of contacts in the connectors linking the two boards. Also, the size and cost of the main board are increased by the presence of the address decoder and the latching register which are part of the second interface.
Finally, the prior art machine has a drawback due to the want of inputs on the input-output circuit. This leads to limiting to five the number of rows in the matrix. As each encoder constitutes a sub-matrix comprising five rows, all of the rows of the matrix are busied when an encoder is scanned. Consequently, the switches are in two groups, independent of the encoders. The states of the switches are transmitted in two bytes separate from the four bytes transmitting the values translated by the four encoders. Six data bytes are therefore transmitted, each containing four wanted bits at most and stuffing bits. This inefficient filling of the data bytes burdens transactions between the interface board and the main board by increasing the number of data bytes.
An object of the invention is to propose a franking machine in which the input-output interface board comprises a single application specific integrated circuit and which does not have the drawbacks of the prior art machine.